Implementation of the Binary Multiplier on CPLD Using Reversible Logic Gates
نویسنده
چکیده
In this paper, we present the Implementation of the Binary Multiplier on CPLD using Reversible logic gates. These circuits have been simulated on Active HDL and synthesised on Xilinx web pack 5.1 software.
منابع مشابه
Reversible Logic Multipliers: Novel Low-cost Parity-Preserving Designs
Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the multiplication is an important operation in computing systems, some novel reversible multiplier designs are propose...
متن کاملA Novel Design of Reversible Multiplier Circuit (TECHNICAL NOTE)
Adders and multipliers are two main units of the computer arithmetic processors and play an important role in reversible computations. The binary multiplier consists of two main parts, the partial products generation circuit (PPGC) and the reversible parallel adders (RPA). This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced PPGC with Peres gates only. Ag...
متن کاملEfficient Reversible Multiplier Circuit Implementation in Fpga
Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. The applications of reversible logic gates include ultralow power, nano computing, quantum computing, low power CMOS design, optical information processing, bioinformatics etc. This paper proposes an improved design of a multiplier usin...
متن کاملDesign of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology
Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterpa...
متن کاملImplementation of an 8-bit Low-power Multiplier based on Reversible Gate Technology
Reversible logic has attracted tremendous interest among the researchers in low power VLSI field due to their simple structure and improved energy efficiency. In this paper, the implementation of an 8-bit low power multiplier based on reversible gate technology is reported. The structure of the reversible gate multiplier consists of following components: the first part is the reversible partial...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2017